Testing a large number of integrated circuit chips in parallel at the wafer level provides significant advantage since test time and cost are substantially reduced. At present, large scale testers including mainframe computers are needed to test even one chip at a time, and the complexity of these machines is increased when the capability of testing arrays of chips in parallel is added. Nevertheless, because of the time savings parallel testing provides, high pin-count testers capable of probing and collecting data from many chips simultaneously have been introduced, and the number of chips that can be tested simultaneously has been gradually increasing.
Wafer level burn-in adds to the difficulty and cost of simultaneous testing since the high pin-count probes must be kept in place on each wafer for many hours and the probes must maintain contact as temperature changes from room temperature to about 140.degree. C. In addition, a scheme to disconnect or limit current to shorted chips is needed to maintain voltage uniformity across the wafer.
Commonly assigned U.S. Pat. No. 5,600,257, to Leas et al. teaches apparatus for simultaneously testing or burning in all the integrated circuit chips on a product wafer. The apparatus comprises a glass ceramic carrier having test chips. Glass ceramic has a thermal coefficient of expansion comparable to that of silicon, enabling probe contact as temperature varies. The test chips provide test patterns. Voltage regulators are on the test chips to provide a specified voltage to the product chips and to limit current to shorted chips. However, glass ceramic carriers large enough to accommodate 8 inch semiconductor wafers are very expensive.
"Known good die," chips that have been individually tested and burned-in after dicing from a wafer, are becoming increasingly available in the industry to provide for multi-chip modules and other applications where high reliability is needed. Burning-in individual chips after dicing avoids the difficulties of contacting and burning-in all chips on a wafer at once. However, there is a substantial cost to handling, aligning, and holding individual chips for burn-in stress over many hours as compared with testing and burning-in at the wafer level.
Substantial lower cost would result from an improved wafer burn-in scheme that permits parallel test and burn-in of the chips on a wafer before dicing without a costly glass ceramic interface, and this solution is provided by the following invention.